Copending application Ser. No. 07/486,407; describes a register file that provides a high performance interface to registers through a multi-ported access structure, allowing four reads and two writes to occur in the same machine cycle on different registers.
Since both register and memory types of instructions are allowed to execute in the same cycle, six possible register requests could be executing. Thus, a 6-port register file design is required to correctly implement these parallel functions.
The RAM design approach of the prior art using true and bar column lines is not desirable because it requires too large a die size. Since the RAM cell must be six-way ported, the true-and-bar-column-lines design would require too much space dedicated only to the metal pitch of the column lines.
It is therefore an object of the present invention to provide a random access memory cell that consumes low power and conforms to a tight layout pitch to meet the needs of a random access memory of a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution.